1. Field of the Invention
The present invention is directed to an improved anti-saturation clamp for use with word decoders. The clamp is particularly useful in connection with Harper/PNP arrays in which large word line swings are required to guarantee array functionality at extreme conditions.
2. Description of the Related Art
In a known two-stage decoder system, commercially available as part of the IBM System 3090 ("IBM" is a registered trademark of the International Business Machines Corporation), the first stage is a regular ECL current switch to handle the initial swing. The second stage completes the word line pull up or drain line pull down by a saturation inversion device comprising a transistor. A resistor is employed as the pull up device to provide the drive for word line selection. When the word line is deselected at the down level, a large current must be pulled down from the resistor through the inversion transistor while the transistor is in saturation, resulting in high saturation capacitance and delay in the word line upswing.
Known anti-saturation clamps that may be used to alleviate these problem can be classified in three (3) different categories, namely: (1) clamps in which base current is diverted to the collector, such as commonly employed SBD clamps; (2) clamps providing brute force voltage bias at the collector node to prevent the collector node from falling into the saturation region, such as cavaliere clamps or other voltage pull up bias circuits; and (3) anti-saturation clamps which combine the two aforementioned devices.
The general state of the prior art with respect to solving the aforementioned high saturation capacitance and related problems may be best illustrated and understood with reference to the several publications and patents to be described immediately hereinafter.
IBM Technical Disclosure Bulletin, Vol. 32, No. 2, pages 272-274 (July, 1989), discloses a high performance word decoder for Harper/PNP cells including a clamping network providing a deselect level which tracks with the select level and the margin needed during write operation. In this system, the depicted LWL levels are clamped to a level that tracks with the Vcc voltage. However, the deselect is slow, many devices are needed for operation of the system, and high standby power is required because the pull down current is from Vcc.
IBM Technical Disclosure Bulletin, Vol. 30, No. 6, page 382-383 (November, 1987), discloses a low power word line driver. However, the system operates very slowly because it employs a PNP pull up.
U.S. Pat. No. 4,494,017, to Montegari, issued Jan. 15, 1985, discloses a decode circuit utilizing NPN and PNP transistors. This system operates very slowly because PNP transistors are employed in the decoder, even though one stage may be reduced. This reference also advocates against the use of any anti-saturation clamps by choosing parameters which will avoid saturation. (See Column 13, line 20-28).
IBM Technical Disclosure Bulletin, Vol. 22, No. 8B, pages 3736-3737 (January, 1980), discloses a two-stage decoder circuit which operates very slowly as a result of saturation operation and pulsing.
IBM Technical Disclosure Bulletin, Vol. 23, No. 9, pages 3747-3748 (January, 1982), discloses a high speed decoder circuit which is a variation of the two-stage decoder circuit (IBM Technical Disclosure Bulletin, Vol. 22, No. 8B, pages 3736-3737), discussed hereinabove. The modified circuit is employed for high density, low power arrays. However, the circuit performance is extremely low, i.e., not acceptable for present day advanced computing applications.
IBM Technical Disclosure Bulletin, Vol. 30, No. 7, page 134 (December, 1987), discloses an up-level clamp for push-pull off chip drivers.
IBM Technical Disclosure Bulletin, Vol. 20, No. 2, pages 562-563 (July, 1978), discloses one form of an array true-complement generator with power drive. This reference, like the aforementioned U.S. Pat. No. 4,494,017, to Montegari, advocates against the use of any anti-saturation clamps.
U.S. Pat. No. 4,394,588, to Gaudenzi, issued Jul. 19, 1983, discloses a circuit driver for limiting the di/dt down transition to minimize di/dt. The system is particularly directed to an off-chip driver for allowing switching of multiple drivers while limiting the di-dt current for down going transition.
U.S. Pat. No. 3,864,484, to Hutson, issued Feb. 4, 1975, discloses a driver circuit employing a PNP transistor which operates slowly. The output device base node levels are controlled with standard SBD (Schottky Barrier Diode) clamps.
None of the aforementioned references, which exemplify the state of the art, teach, claim or even suggest an anti-saturation clamp (or any other anti-saturation means), for use in connection with word decoder systems, which assures that a switching transistor will not operate in saturation to thereby improve system performance by eliminating the delay resulting from saturation capacitance.
Accordingly, it would be desirable to be able to provide a new and improved anti-saturation clamp which eliminates the aforementioned delay resulting from saturation capacitance.
Furthermore, it would be desirable to be able to provide improved word decoder systems that exhibit operating characteristics that are enhanced by virtue of including the improved anti-saturation clamp contemplated by the invention.
Still further, it would be desirable to provide improved methods for enhancing the performance of word decoder systems in general.